List of Items Revised or Added for This Version
Section
Page
Item
Description
1.1 SH7750 Series (SH7750, 1
SH7750S, SH7750R)
Features
Description amended
and added
4 to 8
Table 1.1 SH7750 Series
Features
Description added for
LSI, and description
and Note added for
Clock pulse generator
(CPG)
SH7750 and SH7750S
added to cache memory
Cache memory
[SH7750R] added to
table
Description added for
Direct memory access
controller (DMAC) and
Timer unit (TMU)
SH7750R table added
to Product lineup
Notes 1, 2, 3 added
1.2 Block Diagram
9
Figure 1.1 Block Diagram of I cache 8 KB and 0
SH7750 Series Functions
cache 16 KB deleted
from table
1.3 Pin Arrangement
1.4 Pin Functions
10 to 12
13 to 40
Figure 1.2 to 1.4
SH7750R added, and
description amended
Table 1.2 to 1.4
Table and note
amended
2.7 Processor Modes
55
61
Description deleted
Amended
3.2 Register Descriptions
Figure 3.2 MMU-Related
Registers
62
62
3. Page table entry
assistance register (PTEA)
SH7750R added after
SH7750S
1. Page table entry high
register (PTEH),
Description added
6. MMU control register
(MMUCR)
3.3.1 Physical Address
Space
64 to 67
Description added
Rev. 6.0, 07/02, page v of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
