SERIAL I/O
11.2 Block description
11.2.4 UARTi transmit register and UARTi transmit buffer register
Figure 11.2.5 shows the block diagram for the transmitter; Figure 11.2.6 shows the structure of UARTi
transmit buffer register.
Data bus (odd)
Data bus (even)
UARTi transmit
buffer register
D
8
D
7
D
6
D
5
D
4
D3
D
2
D1
D
0
SP : Stop bit
PAR : Parity bit
8-bit UART
9-bit UART
Clock sync.
7-bit UART
9-bit UART
Clock sync.
Parity
enabled
2SP
1SP
UART
SP
SP
PAR
TxD
i
Parity
disabled
Clock sync.
8-bit UART
7-bit UART
UARTi transmit register
0
Fig. 11.2.5 Block diagram for transmitter
(b8)
b0 b7
(b15)
b7
b0
UART0 transmit buffer register (Addresses 3316, 3216
)
UART1 transmit buffer register (Addresses 3B16, 3A16
)
Bit
Function
At reset R/W
Undefined WO
8 to 0 Transmit data is set.
15 to 9 Nothing is assigned.
Undefined
—
Note: Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register.
Fig. 11.2.6 Structure of UARTi transmit buffer register
7906 Group User’s Manual Rev.2.0
11-10
RENESAS [ RENESAS TECHNOLOGY CORP ]
