SERIAL I/O
11.2 Block description
11.2.3 UARTi transmit/receive control register 1
Figure 11.2.4 shows the structure of UARTi transmit/receive control register 1.
b7 b6 b5 b4 b3 b2 b1 b0
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
Bit
0
Bit name
Function
At reset R/W
0 : Transmission disabled
1 : Transmission enabled
0
RW
Transmit enable bit
Transmit buffer empty flag
Receive enable bit
0 : Data is present in the transmit buffer register
1 : No data is present in the transmit buffer register
1
2
3
4
5
6
7
1
0
RO
0 : Reception disabled
1 : Reception enabled
RW
Receive complete flag
Overrun error flag
0 : No data is present in the receive buffer register
1 : Data is present in the receive buffer register
0
0
0
0
0
RO
RO
RO
RO
RO
0 : No overrun error
1 : Overrun error detected
Framing error flag
(Valid in UART mode)
(Note)
0 : No framing error
1 : Framing error detected
Parity error flag
(Valid in UART mode)
(Note) 0 : No parity error
1 : Parity error detected
0 : No error
1 : Error detected
Error sum flag
(Valid in UART mode)
(Note)
Note: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.
Fig. 11.2.4 Structure of UARTi transmit/receive control register 1
7906 Group User’s Manual Rev.2.0
11-8
RENESAS [ RENESAS TECHNOLOGY CORP ]
