PULSE OUTPUT PORT MODE
9.3 Block description of pulse output port 1
9.3.1 Pluse output control register
Figure 9.3.2 shows the structure of the pluse output control register.
b7 b6 b5 b4 b3 b2 b1 b0
Pluse output control register (Address A016
)
Bit
0
Bit name
Function
At reset R/W
Waveform output select bits
See Table 9.3.1.
0
0
0
RW
RW
RW
(Note)
1
2
0 : Pulse mode 0
1 : Pulse mode 1
0
RW
Pulse output mode select bit
3
Pulse width modulation timer
select bits
0
0
0
RW
RW
RW
4
5
6
See Table 9.3.2.
When pulse mode 0 is selected,
Waveform output control bit 0
Waveform output control bit 1
0: RTP3
1: RTP3
0
to RTP3
to RTP3
3
: pulse outputs are disabled.
: pulse outputs are enabled.
0
3
When pulse mode 1 is selected,
0: RTP3
1: RTP3
2
, RTP3
, RTP3
3
: pulse outputs are disabled.
: pulse outputs are enabled.
2
3
When pulse mode 0 is selected,
7
0
RW
0 : RTP2
0
to RTP2
to RTP2
3
: pulse outputs are disabled.
: pulse outputs are enabled.
1 : RTP2
0
3
When pulse mode 1 is selected,
0 : RTP2
0
to RTP2
3
, RTP30, RTP3
RTP3 , RTP3
.”
1
: pulse outputs
are disabled.
1 : RTP2
0
to RTP2
3
0
1: pulse outputs
are enabled.
Note: When not using pulse output port 1, be sure to fix these bits to “000
2
Fig. 9.3.2 Structure of pluse output control register
7905 Group User’s Manual Rev.1.0
9-16
RENESAS [ RENESAS TECHNOLOGY CORP ]
