RTL8208B-LF/RTL8208BF-LF
Datasheet
7.6.5. Reduced Fiber Interface
The RTL8208BF-LF ignores the underlying SD signal of the fiber transceiver to complete link detection
and connection. This is achieved by monitoring RD signals from the fiber transceiver and checking
whether any link integrity events are encountered. This significantly reduces pin-count, especially for
high-port PHY devices. This is a Realtek patent-pending technology and available only with Realtek
products.
7.7. RMII/SMII/SS-SMII
The interface to the MAC can be RMII, SMII, or SS-SMII through MODE[1:0]. When floating
MODE[1:0] upon power-on reset, the RTL8208B(F)-LF operates in RMII mode (default).
Table 26. RMII/SMII/SS-SMII Modes
MODE[1:0]
2’b1x
Operation Mode
RMII
REFCLK Clock Input
50MHz ±50ppm
2’b00
2’b01
SMII
SS-SMII
125MHz ±50ppm
125MHz ±50ppm
Table 27 illustrates the signals required for each interface:
Table 27. RMII/SMII/SS-SMII Signals
SMII
RMII
REFCLK
SS-SMII
REFCLK
TX_SYNC
REFCLK
SYNC
CRS_DV[2:0]
CRS_DV[3]
CRS_DV[4]
CRS_DV[7:5]
RXD0[7:0]
RXD1[7:0]
TX_EN[3:0]
TX_EN[4]
RX_SYNC
RX_CLK
RXD0[7:0]
TXD0[7:0]
RXD0[7:0]
TX_CLK
TX_EN[7:5]
TXD0[7:0]
TXD1[7:0]
TXD0[7:0]
Single-Chip Octal 10/100-TX/FX PHY Transceiver
33
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
