RTL8208B-LF/RTL8208BF-LF
Datasheet
7.7.2. SMII (Serial MII)
The RTL8208B(F)-LF also supports SMII interface to MAC, which allows a further reduction in the
number of signals. As illustrated below, both the MAC and RTL8208B(F)-LF are synchronous to a
125MHz reference clock.
Figure 4. SMII Signal Diagram
Receive Path
Receive data and control information are signaled in 10-bit segments. The SYNC signal is used to delimit
the 10-bit segments. The MAC is responsible for generating SYNC pulses every ten clocks. In 100Mbps
mode, each segment represents a byte of data. In 10Mbps mode, each segment is repeated ten times to
represent a byte of data. The receive sequence contains all of the information defined on the standard MII
receive path.
Table 28. SMII Reception Encoding
CRS RX_DV
RXD0
RXER
from
Previous
Frame
RXD1
Speed
0: 10Mbps
1: 100Mbps
RXD2
Duplex
0: Half 0: Down
1: Full 1: Up
RXD3
Link
RXD4
Jabber
0: OK
RXD5
Upper
Nibble
0:
Invalid
1: Valid
RXD6
False
Carrier
0: OK
1: Detected
RXD7
X
0
1
1: Detected
X
1
One Data Byte (Two MII Data Nibbles)
1
2
3
4
5
6
7
8
9
10
REFCLK
SYNC
CRS
RXDV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RXD[0]
Figure 5. SMII Reception
Single-Chip Octal 10/100-TX/FX PHY Transceiver
35
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
