RTL8208B-LF/RTL8208BF-LF
Datasheet
7.4.2. Receive Function
The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits. These
circuits compensate for incoming distortion of the MLT-3 signal. An MLT-3 to NRZI, and NRZI to NRZ
converter is used to convert analog signals to digital bit-streams. A PLL circuit is also included to clock
data bits with minimum bit error rate. De-scrambler, 5B/4B decoder, and serial-to-parallel conversion
circuits follow. CRS_DV is asserted no later than within a few bits time of when the SSD (Start-of-
Stream-Delimiter) is detected (delay due to the elastic buffer as mentioned in the RMII section, page 34),
and ends toggling once the data in the elastic buffer has been dumped to RXD.
Table 23. 4B/5B Coding
Name
0
1
2
3
4
5
6
7
4B Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000*
0101*
0101*
0000*
0000*
1000
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
5B Code
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
11000
10001
01101
00111
00100
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Definition
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
8
9
A
B
C
D
E
F
Data F
Idle
I
J
Start of stream Delimiter, Part 1
Start of stream Delimiter, Part 2
End of stream Delimiter, Part 1
End of stream Delimiter, Part 2
Transmit Error (used to force signaling errors)
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
K
T
R
H
V
V
V
V
V
V
V
V
V
V
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
*Treated as an invalid code (mapped to 0111) when received in data field.
Single-Chip Octal 10/100-TX/FX PHY Transceiver
30
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
