RTL8208B-LF/RTL8208BF-LF
Datasheet
7.6.1. Transmit Function
In 100Base-FX transmission, TXD is processed as 100Base-TX, except without scrambling, before the
NRZI stage. Instead of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven
out as NRZI PECL signals. These enter the fiber transceiver in differential-pairs form. The fiber
transceiver only operates in a 3.3V environment. Refer to Figure 22, page 49 for more information.
Table 25. PECL DC Characteristics
Symbol
Min
Max
Unit
Parameter
PECL Input High Voltage
PECL Input Low Voltage
PECL Output High Voltage
PECL Output Low Voltage
Vih
Vil
Voh
Vol
Vdd-1.16
Vdd-1.81
Vdd-1.02
Vdd-0.88
Vdd-1.47
V
V
V
V
Vdd-1.62
7.6.2. Receive Function
Signals are received through PECL receiver inputs from a fiber transceiver and directly passed to a clock
recovery circuit for data/clock recovery. Scrambling/de-scrambling is bypassed in 100Base-FX.
7.6.3. Link Monitor
In 100Base-FX mode, if the RTL8208BF-LF receive path detects a valid link word, it enters the link state.
If no valid link word is detected, it is in a link down state. Therefore, SD+/- is not necessary. The
RTL8208BF-LF uses a reduced 100Base-FX interface.
7.6.4. Far-End-Fault-Indication
The MII Register 1.4 (Remote Fault indication detected) is a Far-End-Fault-Indication (FEFI) bit when
100FX is enabled, and indicates that a FEFI has been detected. FEFI is an alternative in-band signaling
that is composed of 84 consecutive 1’s followed by one 0. When the RTL8208BF-LF has detected this
pattern three times, Reg.1.4 is set, which means the transmit path (Remote side’s receive path) has
problems.
If the RTL8208BF-LF detects no valid link pulse on the RxOP/N pair, it sends out a FEFI stream pattern,
which in turn will cause the remote side to detect a Far-End-Fault. This means the RTL8208BF-LF sees
problems on the receive path.
The FEFI mechanism is used only in 100Base-FX applications.
Single-Chip Octal 10/100-TX/FX PHY Transceiver
32
Track ID: JATR-1076-21 Rev. 1.3