RTL8208B-LF/RTL8208BF-LF
Datasheet
Receive Path
Receive data and control information are signaled in 10-bit segments. The RX_SYNC signal is used to
delimit the 10-bit segments. The RTL8208B(F)-LF is responsible for generating these RX_SYNC pulses
every ten clocks. In 100Mbps mode, each segment represents a byte of data. In 10Mbps mode, each
segment is repeated ten times to represent a byte of data. The receive sequence contains all the
information defined on the standard MII receive path.
1
2
3
4
5
6
7
8
9
10
RX_CLK
RX_SYNC
RXD[0]
CRS
RXDV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
Figure 8. SS-SMII Reception
Transmit Path
Transmit data and control information are signaled in 10-bit segments. The TX_SYNC signal is used to
delimit the 10-bit segments. The MAC is responsible for generating these TX_SYNC pulses every ten
clocks. In 100Mbps mode, each segment represents a byte of data. In 10Mbps mode, each segment is
repeated ten times to represent a byte of data. The receive sequence contains all the information defined
on the standard MII receive path. The PHY can sample one of the ten segments.
1
2
3
4
5
6
7
8
9
10
TX_CLK
TX_SYNC
TXD[0]
TX_ER TX_EN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
Figure 9. SS-SMII Transmission
Collision Detection
The RTL8208B(F)-LF does not indicate that a collision has occurred. It is left to the MAC to detect the
assertion of both CRS_DV and TX_EN.
Single-Chip Octal 10/100-TX/FX PHY Transceiver
37
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
