RTL8208B-LF/RTL8208BF-LF
Datasheet
7.7.1. RMII (Reduced MII)
The RTL8208B(F)-LF meets all of the RMII requirements outlined in the RMII Consortium
specifications. The main advantage introduced by RMII is pin count reduction; e.g., it operates with only
one 50MHz reference clock for both the TX and RX sides, without separate clocks needed for both paths,
as with the MII interface. However, some hardware modification is needed for this change, the most
important of which is the presence of an elastic buffer for absorption of the frequency difference between
the 50MHz reference clock and the clocking information of the incoming data stream. Another change
implemented is that the MII RXDV and Carrier_Sense are merged into one signal, CRS_DV, which is
asserted high while detecting incoming packet data. When internal Carrier_Sense is de-asserted,
CRS_DV is de-asserted when the first di-bit of a nibble is presented onto RXD[1:0] synchronously to
REFCLK. If there is still data in the FIFO that has not yet been presented onto RXD[1:0], then, on the
second di-bit of a nibble, CRS_DV reasserts. This pattern of assertion and de-assertion continues until all
received data in the FIFO has been presented onto RXD[1:0]
Figure 3. RMII Signal Diagram
Single-Chip Octal 10/100-TX/FX PHY Transceiver
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Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
