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SM2604T-6 参数 Datasheet PDF下载

SM2604T-6图片预览
型号: SM2604T-6
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 4MX16, 4.3ns, CMOS, PDSO54, TSOP-54]
分类和应用: 时钟动态存储器光电二极管
文件页数/大小: 33 页 / 305 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号SM2604T-6的Datasheet PDF文件第15页浏览型号SM2604T-6的Datasheet PDF文件第16页浏览型号SM2604T-6的Datasheet PDF文件第17页浏览型号SM2604T-6的Datasheet PDF文件第18页浏览型号SM2604T-6的Datasheet PDF文件第20页浏览型号SM2604T-6的Datasheet PDF文件第21页浏览型号SM2604T-6的Datasheet PDF文件第22页浏览型号SM2604T-6的Datasheet PDF文件第23页  
64Mbit – Enhanced SDRAM  
8Mx8, 4Mx16 ESDRAM  
Preliminary Datasheet  
Clock and Clock Enable Parameters  
Symbol  
Parameter  
-6  
-7.5  
-10  
Units  
Notes  
Min  
6
12  
-
-
-
2.4  
5
1.5  
0.8  
1.5  
-
Max  
166MHz  
Min  
7.5  
15  
-
-
-
2.8  
6
1.5  
0.8  
1.5  
-
Max  
133MHz  
Min  
10  
15  
-
-
-
3.5  
6
2.0  
1.0  
2.0  
-
Max  
100MHz  
tCK2  
tCK1  
tAC3  
tAC2  
Clock Cycle Time, CL = 2, 3  
Clock Cycle Time, CL = 1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
83MHz  
66MHz  
66MHz  
Clock Access Time, CL = 3  
Clock Access Time, CL = 2  
Clock Access Time, CL = 1  
Clock High & Low Times, CL = 2, 3  
Clock High & Low Times, CL = 1  
Clock Enable Set-Up Time  
Clock Enable Hold Time  
CKE Set-Up Time (Power down mode)  
Transition Time (Rise and Fall)  
4.3  
4.6  
10.5  
-
-
-
-
-
2
4.5  
4.8  
11  
-
-
-
-
-
3
4.7  
5.0  
11.5  
-
-
-
-
-
3
1, 2  
1, 2  
1, 2  
3
tAC1  
tCKH2, tCKL2  
tCKH1, tCKL2  
tCKES  
tCKEH  
tCKSP  
3
tT  
Notes:  
1. Access time is measured at 1.4V (LVTTL) and VDDQ = 3.3V +10%, -5%. See AC Test Load.  
2. Access time is based on a clock rise time of 1ns. If clock rise time is longer than 1ns, then (trise/2 - 0.5) ns must be added to the access time.  
3. Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, other AC timing parameters must be compensated by an  
additional [(trise+tfall)/2 - 1] ns.  
Common Parameters  
Symbol  
Parameter  
-6  
-7.5  
-10  
Units  
Notes  
Min  
1.5  
0.8  
12  
30  
18  
12  
12  
6
Max  
Min  
1.5  
0.8  
15  
37.5  
22.5  
15  
15  
7.5  
2
Max  
Min  
2.0  
1.0  
15  
45  
30  
15  
15  
10  
2
Max  
tCS  
tCH  
Command and Address Set-Up Time  
Command and Address Hold Time  
RAS to CAS Delay Time  
Bank Cycle Time  
Bank Active Time  
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
clk  
tRCD  
tRC  
tRAS  
tRP  
tRRD  
tCCD  
tMRD  
120K  
120K  
120K  
Precharge Time  
-
-
-
-
-
-
-
-
-
-
-
-
Bank to Bank Delay Time (Alt. Bank)  
CAS to CAS Delay Time (Same Bank)  
Mode Register Set to Active Delay  
2
This is a product in sampling or pre-production phase of development. Charac-  
teristic data and other specifications are subject to change without notice.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
Revision 1.1  
Page 19 of 33  
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