64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Burst Reads (CL = 2, BL = 4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRCD
tRP
tRCD
tRP
tRAS
tRAS
tRC
CS#
RAS#
CAS#
WE#
B0
R0
R0
R0
B0
C0
B0
R1
R1
R1
B0
B0
BA(1:0)
A11, A9
A10/AP
A(8:0)
DQM
C4
Q3
C8
Q6
Q0
Q1
Q2
Q4
Q5
Q7
Q8
Q9
Q10
Q11
DQ
Internal Status
All Banks
Active
Precharge
Active
Precharge
Idle
R0
R1
Cache 0
In CL2 mode the ESDRAM delivers worst-case burst read data with only one wait state at clock rates up to 166 MHz.
This high performance is achieved through a combination of fast DRAM core timings and use of the SRAM row cache.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Revision 1.1
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