64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Timing Diagrams (B = Bank Address, R = Row Address, C = Column Address)
Power Up and Initialization Sequence
CLK
tRP
tRC
tRC
tMRD
tMRD
CS#
RAS#
CAS#
WE#
00
10
Bx
R
BA(1:0)
A11, A9
A10/AP
A(8:0)
Code
Code
R
Code
Code
R
DQM
Hi-Z
DQ
Internal Status
All Banks
Precharge All
Refresh
Refresh
MRS
EMRS
Bank X Active
After Power is applied to VDD and VDDQ, and the clock is stable, an initial pause of 100µs is required. Once this delay is
satisfied, the controller must issue DESEL commands prior to the signaling shown in this diagram. The EMRS command
is optional.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Revision 1.1
Page 21 of 33
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
