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SM2604T-6 参数 Datasheet PDF下载

SM2604T-6图片预览
型号: SM2604T-6
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 4MX16, 4.3ns, CMOS, PDSO54, TSOP-54]
分类和应用: 时钟动态存储器光电二极管
文件页数/大小: 33 页 / 305 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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64Mbit – Enhanced SDRAM  
8Mx8, 4Mx16 ESDRAM  
Preliminary Datasheet  
Operating Currents (TA = 0°C to 70°C, VDD = 3.3V +10%, -5%)  
Parameter  
Symbol  
Test Condition  
Value  
-7.5  
Units  
Notes  
-6  
-10  
ICC1A  
ICCB  
ICC2P  
ICC2PS  
BL = 1, CL = 1, Read or Write,  
190  
165  
160  
mA  
mA  
mA  
mA  
1,3  
1,3  
CKE VIH(min), tRC = min., tCK = min.  
Operating Current  
(One Bank Active)  
BL = 1, CL = 2,3, Read or Write,  
CKE VIH(min), tRC = min., tCK = min.  
250  
2
210  
2
175  
2
CKE VIL, tCK = min.,  
Standby Current in  
Power Down Mode  
(DRAM Precharged)  
Input Change Every Two Cycles  
1.5  
1.5  
1.5  
CKE VIL, tCK = Infinity,  
No Input Change  
Standby Current in Non-  
Power Down Mode  
ICC2N  
90  
15  
80  
15  
70  
15  
mA  
mA  
CKE VIH, tCK = min.  
CKE VIH, tCK = Infinity  
ICC2NS  
(DRAM Precharged)  
ICC3N  
ICC3P  
ICC4A  
ICC4B  
100  
90  
80  
mA  
CKE VIH, tCK = min.,  
Input Change Every Two Cycles  
Device Deselected  
(DRAM Active)  
3
2.5  
2
mA  
CKE VIL, tCK = min.,  
Input Change Every Two Cycles  
BL = Full Page, CL = 1, Read or Write,  
170  
300  
140  
280  
130  
270  
mA  
mA  
1,2,3  
1,2,3  
tRC = Infinity, tCK = min.  
Burst Operating Current  
(All Banks Active)  
BL = Full Page, CL = 2,3, Read or Write,  
tRC = Infinity, tCK = min.  
ICC5F  
ICC5D  
ICC6  
CL = 3, tCK = min., tRC = tRC(min).  
CL = 3, tCK = min., tRC = 15.625 µs  
CKE 0.2V, No Input Change  
380  
40  
2.5  
340  
35  
2.5  
310  
30  
2.5  
mA  
mA  
mA  
3,4,5  
3,4,5  
Auto (CBR) Refresh  
Current  
Self Refresh Current  
Notes:  
1. The specified value is obtained with the outputs open.  
2. The specified value is obtained when the programmed burst length is executed to completion without interruption by a subsequent burst read or  
burst write cycle.  
3. The specified value is valid when addresses are changed no more than once during tCK(min).  
4. The specified value is valid when No Operation commands are registered on every rising clock edge during tRC(min).  
5. The specified value is valid when data inputs (DQs) are stable during tRC(min).  
This is a product in sampling or pre-production phase of development. Charac-  
teristic data and other specifications are subject to change without notice.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
Revision 1.1  
Page 17 of 33  
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