FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Stop
Start
S
Address & Data
By Master
By F-RAM
Slave Address
0
A
Address MSB
A
Address LSB
A
Data Byte
A
P
Acknowledge
Figure 5. Single Byte Write
Start
S
Stop
P
Address & Data
Address MSB
By Master
By F-RAM
Slave Address
0
A
A
Address LSB
A
Data Byte
A
Data Byte
A
Acknowledge
Figure 6. Multiple Byte Write
Each time the bus master acknowledges a byte,
this indicates that the FM24CL64B should read
out the next sequential byte.
Read Operation
There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24CL64B uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most likely create
a bus contention as the
FM24CL64B attempts to read out additional data
onto the bus. The four valid methods are:
Current Address & Sequential Read
1. The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.
As mentioned above the FM24CL64B uses an
internal latch to supply the address for a read
operation. A current address read uses the existing
value in the address latch as a starting place for the
read operation. The system reads from the address
immediately following that of the last operation.
2. The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
3. The bus master issues a stop in the 9th clock
cycle.
To perform a current address read, the bus master
supplies a slave address with the LSB set to a „1‟.
This indicates that a read operation is requested.
After receiving the complete slave address, the
FM24CL64B will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.
4. The bus master issues a start in the 9th clock
cycle.
If the internal address reaches 1FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 below show the proper operation for current
address reads.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
Rev. 1.1
June 2011
Page 6 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
