QN8007B/8007LB
6.3 I2S Interface Timing Description
The word select line indicates the channel being transmitted:
WS = 0; channel 1 (left);
WS = 1; channel 2 (right).
WS sent by the transmitter is synchronized by the trailing (HIGH-to-LOW) edge of the serial clock signal and is latched
into the receiver on the leading (LOW-to-HIGH) edge of the serial clock signal.
The serial data signal SD has the same timing requirement as the WS signal. It is sent on the trailing edge of the clock signal
by the transmitter, and received on the leading edge of the clock signal by the receiver. The serial data is transmitted in
two’s complement with the MSB first. The MSB is transmitted first because the transmitter and the receiver may have
different word lengths. There are four data word lengths supported by the QN8007; 8, 16, 24 and 32.
There are five data alignment modes supported by QN8007. The detailed timing descriptions are shown as below.
6.3.1 MSB-Justified (Format 0)
MCK
WS
DIN
(Left)
(Right)
N-1 N-2 N-3
0
N-1 N-2 N-3
0
N-1
The transmitter sends the MSB (N-1) bit of the next word when the WS changes and sends the second MSB bit in the next
clock period. Each bit is sent by the transmitter in one clock period until the LSB (0) bit is sent. The N indicates the word
length that can be 8, 16, 24, and 32.
6.3.2 I2S (Format 1)
The transmitter sends the MSB(N-1) bit of the next word one clock period after the WS changes and sends the second MSB
bit in the next clock period. Each bit is sent by the transmitter in one clock period until the LSB (0) bit is sent. In the case
that the number of cycles equal the number of bits to be sent, the LSB (0) bit could be sent after the next WS change. The N
indicates the word length that can be 8, 16, 24, and 32.
6.3.3 DSP1 (Format 2)
Rev 2.09 (11/09)
Confidential A
Copyright ©2009 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
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