QN8007B/8007LB
Register Bit R/W Status:
RO - Read Only: You can not program these bits.
WO - Write Only: You can write and read these bits; the value you read back will be the same as written.
R/W - Read/Write: You can write and read these bits; the value you read back can be different from the value
Typically, the value is set by the chip itself. This could be a calibration result, AGC FSM result, etc.
written.
Word: SYSTEM1
Address: 00h
Bit 7
(MSB)
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
rsvd
txreq
wo
chsc
wo
stnby
wo
rsvd
wo
txi2s
wo
rdsen
wo
cca_ch_dis
wo
wo
Bit
Symbol
rsvd
Default
Description
7
6
0
0
Reserved
TXREQ
Transmission request:
0
1
Non TX mode. Either idle or standby mode.
Enter Transmit mode.
5
CHSC
0
Channel Scan mode enable: Combined with TXREQ, the chip scans for an
empty channel for transmission. After completing channel scanning, this bit
will be cleared automatically.
For CCS (TX Scan), the clearest channel (channel with weakest RSSI) will
be selected (if TXCCAA is not equal zero, another prior condition should
be met, see description of CCA register at 19h).To use the scanned channel,
set CCA_CH_DIS to 0. (CCA_CH_DIS can be set to 0 at the same time
CHSC=1).
0
1
Normal operation.
Channel Scan mode operation.
4
STNBY
0
Request immediately to enter Standby mode if the chip is in IDLE and no
TXREQ is received.
0
Non standby mode. Either idle, or TX mode.
Enter standby mode.
1
3
2
rsvd
0
0
Reserved
I2S enable:
TXI2S
0
1
Use analog input for TX audio.
Use I2S digital signal for TX audio.
1
0
RDSEN
0
1
RDS enable:
0
1
RDS disable.
RDS enable.
CCA_CH_DIS
CH (channel index) selection method: See description for CH register at
08h and 0Bh for more information.
0
CH is determined by internal CCA (channel scan).
Rev 2.09 (11/09)
Confidential A
Copyright ©2009 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
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