QN8007B/8007LB
1
CH is determined by the content in CH[9:0].
Note: TXREQ has highest priority, and STNBY has the lowest priority.
Word: SYSTEM2
Address: 01h
Bit 7
Bit 6
Bit 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSB)
(LSB)
tmout[0]
wo
swrst
wo
recal
wo
rsvd
wo
st_mo_tx
wo
tc
rdstxrdy
wo
tmout[1]
wo
wo
Bit
Symbol
Default
Description
7
SWRST
0
Reset all registers to default values:
0
1
Keep the current value.
Reset to default values.
6
RECAL
0
Reset the state to initial states and recalibrate all blocks:
0
1
FSM runs normally.
Reset the FSM. After this bit is de-asserted, FSM will go through
all the power up and calibration sequence.
5
4
rsvd
0
0
Reserved
ST_MO_TX
TX stereo and mono mode selection:
0
1
Stereo
Mono
3
TC
1
Pre-emphasis time constant: (µs)
0
1
50
75
2
RDSTXRDY
TMOUT[1:0]
0
RDS transmit ready: Toggle this bit to transmit all 8 bytes in RDS0~RDS7.
The chip will internally fetch these bytes after completing transmit of the
current group.
1:0
01
Time out setting for IDLE to standby state transition: (min)
0 0
0 1
1 0
1 1
1
3
5
infinity (never)
Rev 2.09 (11/09)
Confidential A
Copyright ©2009 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
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