Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 15
Speed Grade Definition Speed Bins for DDR2-400B
Speed Grade
DDR2–400B
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–5
3–3–3
tCK
—
Parameter
Symbol
Min.
Max.
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
5
8
tCK
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
40
55
15
15
70000
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
.
3.3.2
Component AC Timing Parameters
Timing Parameters for: DDR2–800(Table 16), DDR2–667(Table 17), DDR2–533C(Table 18) and DDR2–400B(Table 19)
TABLE 16
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
9)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
tAC
–400
2
+400
—
ps
tCCD
nCK
tCK.AVG
ps
10)11)
10)11)
12)
tCH.AVG
tCK.AVG
0.48
2500
3
0.52
8000
—
CKE minimum pulse width ( high and low pulse tCKE
nCK
width)
10)11)
13)14)
Average clock low pulse width
tCL.AVG
0.48
0.52
—
tCK.AVG
nCK
ns
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
––
19)20)15)
DQ and DM input hold time
tDH.BASE
125
––
ps
Rev. 1.3, 2006-12
20
03292006-6GMD-RSFT
QIMONDA [ QIMONDA AG ]
