Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
26) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the
max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
9)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
tAC
–450
2
+450
—
ps
tCCD
nCK
tCK.AVG
ps
10)11)
12)
tCH.AVG
tCK.AVG
0.48
3000
3
0.52
8000
—
CKE minimum pulse width ( high and low pulse tCKE
nCK
width)
10)11)
13)14)
Average clock low pulse width
tCL.AVG
0.48
0.52
—
tCK.AVG
nCK
ns
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
—
19)20)15)
9)
DQ and DM input hold time
tDH.BASE
tDIPW
tDQSCK
tDQSH
175
—
ps
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
0.35
–400
0.35
0.35
—
—
tCK.AVG
ps
+400
—
tCK.AVG
tCK.AVG
ps
DQS input low pulse width
tDQSL
—
16)
17)
DQS-DQ skew for DQS & associated DQ signals tDQSQ
240
+ 0.25
DQS latching rising transition to associated clock tDQSS
– 0.25
tCK.AVG
edges
Rev. 1.3, 2006-12
23
03292006-6GMD-RSFT
QIMONDA [ QIMONDA AG ]
