Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol
DDR2–667
Min.
Unit
Note
1)2)3)4)5)6)7)8)
Max.
18)19)20)
17)
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
tDS.BASE
tDSH
100
0.2
0.2
—
—
—
—
ps
tCK.AVG
tCK.AVG
ps
17)
tDSS
21)
tHP
Min(tCH.ABS,
tCL.ABS
)
9)22)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
25)23)
tIH.BASE
275
0.6
ps
Control & address input pulse width for each input tIPW
—
tCK.AVG
ps
24)25)
9)22)
9)22)
31)
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
tIS.BASE
200
—
tLZ.DQ
tLZ.DQS
tMOD
tMRD
tOIT
2 x tAC.MIN
tAC.MAX
tAC.MAX
12
ps
tAC.MIN
ps
0
2
0
ns
—
nCK
ns
31)
12
26)
tQH
t
HP – tQHS
—
ps
27)
tQHS
—
340
1.1
0.6
—
ps
28)29)
28)30)
31)
Read preamble
tRPRE
tRPST
tRTP
0.9
0.4
7.5
0.35
0.4
15
tCK.AVG
tCK.AVG
ns
Read postamble
Internal Read to Precharge command delay
Write preamble
tWPRE
tWPST
tWR
—
tCK.AVG
tCK.AVG
ns
Write postamble
0.6
—
31)
Write recovery time
31)32)
Internal write to read command delay
Exit power down to read command
tWTR
tXARD
7.5
2
—
ns
—
nCK
nCK
Exit active power-down mode to read command tXARDS
7 – AL
—
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
31)
Exit self-refresh to a non-read command
Exit self-refresh to read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
nCK
nCK
Write command to DQS associated clock edges WL
RL–1
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
Rev. 1.3, 2006-12
24
03292006-6GMD-RSFT
QIMONDA [ QIMONDA AG ]
