Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Parameter
Symbol
- 6
- 7.5
Unit Note
min.
42
max.
min.
max.
70,000 ns
1)2)3)21)
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
tRAS
tRC
70,000 45
1)2)3)21)
1)2)3)21)
60
72
–
–
65
75
–
–
ns
ns
AUTO REFRESH to ACTIVE/AUTO REFRESH
command period
tRFC
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)22)
1)2)3)
ACTIVE to READ or WRITE delay
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B delay
WRITE recovery time
tRCD
tRP
tRRD
tWR
18
18
12
15
–
–
–
–
22.5
22.5
15
–
–
–
–
ns
ns
ns
ns
tCK
tCK
ns
ns
tCK
ms
µs
15
Auto precharge write recovery + precharge time
Internal write to Read command delay
Self refresh exit to next valid command delay
Exit power down delay
tDAL
tWTR
tXSR
tXP
1
–
1
–
1)2)3)21)
1)2)3)
120
–
120
–
t
CK+ tIS
–
t
CK+ tIS
–
1)2)3)
CKE minimum high or low time
Refresh period
tCKE
tREF
tREFI
2
–
–
–
2
–
–
–
1)2)3)
64
7.8
64
7.8
1)2)3)23)
Average periodic refresh interval (8192 rows)
1) All parameters assume proper device initialization.
2) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals
other than CK/CK is VDDQ/2.
3) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
4) The output timing reference level is VDDQ/2.
5) Parameters tAC and tDQSCK are specified for full drive strength and a reference load (see Figure 40). This circuit is not intended to be either
a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half
drive strength with a nominal load of 10pF parameters tAC and tDQSCK are expected to be in the same range. However, these parameters
are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation
is suggested.
6) Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
7)tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).
tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one
transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data ball skew
and output pattern effects, and p-channel to n-channel variation of the output drivers.
8) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
9) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling).
10) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
11) Input slew rate ≥ 1.0 V/ns.
12) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
13) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test.
14) The transition time for address and command inputs is measured between VIH and VIL.
15) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
16) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
17)tDQSQ consists of data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
given cycle.
18) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
Rev.1.0, 2007-03
56
10242006-Y557-TZXW
QIMONDA [ QIMONDA AG ]
