Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Parameter & Test Conditions
Symbol
IDD3P
Values
- 6
Values
- 7.5
Unit Note1)2)
3)4)
Active power-down standby current:
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
4
4
mA
mA
Active power-down standby current with clock stop:
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are
STABLE
IDD3PS
3.0
3.0
Active non power-down standby current:
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
IDD3N
50
44
mA
mA
Active non power-down standby current with clock stop:
one bank active, CKE is HIGH, CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are
STABLE
IDD3NS
5.0
5.0
5)
Operating burst read current:
IDD4R
130/125/110 100/90/80 mA
135/130/115 100/90/80 mA
one bank active; BL = 4; CL = 3; tCK = tCKmin; continuous read bursts;
IOUT = 0 mA; address input are SWITCHING; 50% data change each
burst transfer
5)
Operating burst write current:
one bank active; BL = 4; tCK = tCKmin; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
IDD4W
IDD5
IDD6
IDD8
Auto-Refresh current:
370
270
mA
µA
µA
t
RC = tRFCmin; tCK = tCKmin; burst refresh; CKE is HIGH; address and
control inputs are SWITCHING; data bus inputs are STABLE
Self refresh current:
CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are
STABLE; data bus inputs are STABLE
see
see
Table 27
Table 27
Deep Power Down current
506)
1) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for -7.5 speed grade.
2) Input slew rate is 1.0 V/ns.
3) Definitions for IDD:
LOW is defined as VIN ≤ 0.1 * VDDQ
;
HIGH is defined as VIN ≥ 0.9 * VDDQ
;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- address and command: inputs changing between HIGH and LOW once per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE
4) All parameters are measured with no output loads.
5) Assuming one of the die is in active RD/WR, whereas the other is in X/Y/Z mode, where X is active non Power-Down standby, Y is
precharge non Power-Down standby, and Z is active Power-Down standby. Note, X/Y scenarios apply to 1CKE or 2CKE options; whereas
Z is only applicable for 2CKE option.
6)
IDD8 value shown as typical.
Rev.1.0, 2007-03
59
10242006-Y557-TZXW
QIMONDA [ QIMONDA AG ]
