Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Parameter
Symbol
- 6
- 7.5
max.
Unit
Note
min.
max.
0.6
min.
7)
Write postamble
tWPST
0.4
0.25
42
60
18
15
1
0.4
0.6
–
tCK
tCK
Write preamble
tWPRE
tRAS
tRC
–
0.25
–
8)
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
WRITE recovery time
70,000 45
70,000 ns
8)
8)
8)
–
–
–
–
–
65
–
–
–
–
–
ns
ns
ns
tCK
ns
tRCD
tWR
tWTR
tRP
22.5
15
Internal write to Read command delay
PRECHARGE command period
1
–
8)
18
22.5
1) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling).
2) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
3) Input slew rate ≥ 1.0 V/ns.
4) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
5) This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
6) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
7) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
8) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
During WRITE bursts, the first valid data-in element is registered on the first rising edge of DQS following the WRITE command,
and subsequent data elements are registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is
known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS
)
is specified with a relatively wide range (from 75% to 125% of a clock cycle). The diagrams in Figure 24 show the two extremes
of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain
High-Z and any additional input data is ignored.
Rev.1.0, 2007-03
33
10242006-Y557-TZXW
QIMONDA [ QIMONDA AG ]
