Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 23
Basic WRITE Timing Parameters for DQs
tCK
tCH
tCL
CK
CK
tDSH
tDSH
Case 1:
tDQSS = min
tDQSS
tDQSH
tWPST
DQS
tWPRES
tDQSL
tWPRE
tDS
tDH
DQ, DM
DI n
tDSS
tDSS
Case 2:
tDQSS = max
tDQSS
tDQSH
tWPST
DQS
tWPRES
tDQSL
tWPRE
tDH
tDS
DQ, DM
DI n
DI n = Data In for column n
Burst Length = 4 in the case shown
= Don't Care
3 subsequent elements of Data In are applied in the programmed order following DI n.
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS
must fall within the ± 25% window of the corresponding positive clock edge.
TABLE 12
Timing Parameters for WRITE Command
Parameter
Symbol
- 6
- 7.5
Unit
Note
min.
max.
min.
max.
1)2)3)
1)2)4)
1)2)3)
1)2)4)
5)
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
fast slew rate
slow slew rate
fast slew rate
slow slew rate
tDS
0.6
–
–
–
–
–
0.75
0.85
0.75
0.85
1.7
–
–
–
–
–
ns
ns
TBD
0.6
tDH
TBD
2.1
tDIPW
tDQSS
tDQSH
tDQSL
tDSS
ns
Write command to 1st DQS latching transition
DQS input high-level width
0.75 1.25
0.75 1.25
tCK
tCK
tCK
tCK
tCK
ns
–
–
–
–
0.4
0.4
0.2
0.2
0
0.6
0.6
–
0.4
0.4
0.2
0.2
0
0.6
0.6
–
DQS input low-level width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write preamble setup time
tDSH
–
–
–
6)
tWPRES
–
–
Rev.1.0, 2007-03
32
10242006-Y557-TZXW
QIMONDA [ QIMONDA AG ]
