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HYB25D512160BE-5 参数 Datasheet PDF下载

HYB25D512160BE-5图片预览
型号: HYB25D512160BE-5
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.5ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66]
分类和应用: 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 37 页 / 1337 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB25D512[40/16/80]0B[E/F/C/T](L)  
Double-Data-Rate SDRAM  
TABLE 16  
Electrical Characteristics and DC Operating Conditions  
Parameter  
Symbol  
Values  
Unit Note/Test Condition 1)  
Min.  
Typ.  
Max.  
Device Supply Voltage  
Device Supply Voltage  
Output Supply Voltage  
Output Supply Voltage  
EEPROM supply voltage  
VDD  
2.3  
2.5  
2.3  
2.5  
2.3  
0
2.5  
2.6  
2.5  
2.6  
2.5  
2.7  
2.7  
2.7  
2.7  
3.6  
0
V
V
V
V
V
V
fCK 166 MHz  
CK > 166 MHz 2)  
fCK 166 MHz 3)  
CK > 166 MHz 2)3)  
VDD  
f
VDDQ  
VDDQ  
VDDSPD  
f
Supply Voltage, I/O Supply  
Voltage  
VSS,  
VSSQ  
4)  
5)  
Input Reference Voltage  
VREF  
VTT  
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ  
V
V
I/O Termination Voltage  
(System)  
V
REF – 0.04  
V
REF + 0.04  
6)  
6)  
6)  
Input High (Logic1) Voltage VIH(DC)  
V
REF + 0.15  
V
V
V
DDQ + 0.3  
REF – 0.15  
DDQ + 0.3  
V
V
V
Input Low (Logic0) Voltage  
VIL(DC)  
VIN(DC)  
0.3  
0.3  
Input Voltage Level,  
CK and CK Inputs  
6)7)  
8)  
Input Differential Voltage,  
CK and CK Inputs  
VID(DC)  
0.36  
0.71  
–2  
V
DDQ + 0.6  
V
VI-Matching Pull-up Current VIRatio  
to Pull-down Current  
1.4  
2
μA  
Input Leakage Current  
II  
Any input 0 V VIN VDD;  
All other pins not under test  
= 0 V 9)  
Output Leakage Current  
IOZ  
–5  
5
μA  
DQs are disabled;  
0 V VOUT VDDQ  
9)  
Output High Current, Normal IOH  
Strength Driver  
–16.2  
mA VOUT  
=
1.95 V  
Output Low Current, Normal IOL  
16.2  
mA OUT = 0.35 V  
V
Strength Driver  
1) 0 °C TA 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);  
2) DDR400 conditions apply for all clock frequencies above 166 MHz  
3) Under all conditions, VDDQ must be less than or equal to VDD  
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ  
5) TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and  
must track variations in the DC level of VREF  
6) Inputs are not recognized as valid until VREF stabilizes.  
7) ID is the magnitude of the difference between the input level on CK and the input level on CK.  
.
.
V
.
V
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and  
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between  
pull-up and pull-down drivers due to process variation.  
9) Values are shown per pin.  
Rev. 1.70, 2007-11  
24  
03062006-PFFJ-YJY2  
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