Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
7)
t
HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on tDQSS
.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
12)
TABLE 18
AC Timing - Absolute Specifications
Parameter
Symbol
–7
DDR266A
Unit
Note/Test
Condition1)
Min.
Max.
2)3)4)5)
2)3)4)5)
DQ output access time from CK/CK
CK high-level width
tAC
tCH
tCK
–0.75
+0.75
0.55
12
ns
tCK
ns
ns
ns
tCK
tCK
ns
ns
ns
tCK
ns
tCK
ns
tCK
tCK
ns
ns
ns
0.45
Clock cycle time
7.5
CL = 3.02)3)4)5)
CL = 2.52)3)4)5)
CL = 2.02)3)4)5)
7.5
12
7.5
12
2)3)4)5)
CK low-level width
tCL
0.45
0.55
—
2)3)4)5)6)
2)3)4)5)
Auto precharge write recovery + precharge time
DQ and DM input hold time
tDAL
(tWR/tCK)+(tRP/tCK)
tDH
0.5
—
2)3)4)5)6)
2)3)4)5)
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
tDIPW
tDQSCK
tDQSL,H
1.75
–0.75
0.35
—
—
+0.75
—
2)3)4)5)
DQS-DQ skew (DQS and associated DQ signals) tDQSQ
Write command to 1st DQS latching transition
+0.5
1.25
—
TSOPII 2)3)4)5)
2)3)4)5)
tDQSS
tDS
0.75
0.5
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)7)
DQ and DM input setup time
DQS falling edge hold time from CK (write cycle) tDSH
0.2
—
DQS falling edge to CK setup time (write cycle)
Clock Half Period
tDSS
tHP
tHZ
tIH
0.2
—
min. (tCL, tCH
–0.75
)
Data-out high-impedance time from CK/CK
Address and control input hold time
+0.75
—
0.9
fast slew rate
3)4)5)6)8)
1.0
—
ns
slow slew rate
3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse width (each input)
Address and control input setup time
tIPW
tIS
2.2
0.9
—
—
ns
ns
fast slew rate
3)4)5)6)8)
1.0
—
ns
slow slew rate
3)4)5)6)8)
Rev. 1.70, 2007-11
28
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
