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HYB25D512160BE-5 参数 Datasheet PDF下载

HYB25D512160BE-5图片预览
型号: HYB25D512160BE-5
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.5ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66]
分类和应用: 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 37 页 / 1337 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB25D512[40/16/80]0B[E/F/C/T](L)  
Double-Data-Rate SDRAM  
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.  
11) Requires appropriate DM masking.  
TABLE 12  
Truth Table 4: Current State Bank n - Command to Bank m (different bank)  
Current State  
CS  
RAS CAS WE Command  
Action  
Notes  
1)2)3)4)5)6)  
Any  
H
L
X
H
X
X
H
X
X
H
X
Deselect  
NOP. Continue previous operation.  
1) to 6)  
1) to 6)  
No Operation  
NOP. Continue previous operation.  
Idle  
X
Any Command  
Otherwise Allowed to  
Bank m  
1) to 6)  
Row Activating,  
Active, or Pre  
charging  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
L
Active  
Select and activate row  
Select column and start Read burst  
Select column and start Write burst  
1) to 7)  
H
H
L
Read  
1) to 7)  
L
Write  
1) to 6)  
H
H
L
L
Precharge  
Active  
1) to 6)  
Read (Auto  
Precharge  
Disabled)  
L
H
H
L
Select and activate row  
Select column and start new Read burst  
1) to 7)  
H
L
Read  
1) to 6)  
H
H
L
Precharge  
Active  
1) to 6)  
Write (Auto  
Precharge  
Disabled)  
L
H
H
L
Select and activate row  
Select column and start Read burst  
Select column and start new Write burst  
1) to 8)  
H
H
L
Read  
1) to 7)  
L
Write  
1) to 6)  
H
H
L
L
Precharge  
Active  
1) to 6)  
Read (With Auto  
Precharge)  
L
H
H
L
Select and activate row  
Select column and start new Read burst  
Select column and start Write burst  
1) to 7), 9)  
1) to 7), 9), 10)  
1) to 6)  
H
H
L
Read  
L
Write  
H
H
L
L
Precharge  
Active  
1) to 6)  
Write (With Auto  
Precharge)  
L
H
H
L
Select and activate row  
Select column and start Read burst  
Select column and start new Write burst  
1) to 7), 9)  
1) to 7), 9)  
1) to 6)  
H
H
L
Read  
L
Write  
H
L
Precharge  
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 10: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if  
the previous state was self refresh).  
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those  
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in  
the notes below.  
3) Current state definitions:  
Idle: The bank has been precharged, and tRP has been met.  
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in  
progress.  
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.  
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.  
Read with Auto Precharge Enabled: See 10)  
Write with Auto Precharge Enabled: See 10)  
.
.
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.  
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.  
6) All states and sequences not shown are illegal or reserved.  
Rev. 1.70, 2007-11  
20  
03062006-PFFJ-YJY2  
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