Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 15
Input and Output Capacitances
Parameter
Symbol
Values
Min. Typ. Max.
Unit Note/ Test Condition
Input Capacitance: CK, CK
CI1
1.5
2.0
—
—
—
—
—
—
—
—
—
—
2.5
3.0
0.25
2.5
3.0
0.5
4.5
5.0
0.5
pF
pF
pF
pF
pF
pF
pF
pF
pF
TSOPII 1)
TFBGA 1)
1)
Delta Input Capacitance
CdI1
CI2
Input Capacitance: All other input-only pins
1.5
2.0
—
TFBGA 1)
TSOPII 1)
1)
Delta Input Capacitance: All other input-only pins CdIO
Input/Output Capacitance: DQ, DQS, DM
CIO
3.5
4.0
—
TFBGA 1)2)
TSOPII 1)2)
1)
Delta Input/Output Capacitance: DQ, DQS, DM
CdIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f= 100 MHz, TA = 25 °C, VOUT(DC)
= VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
Rev. 1.70, 2007-11
23
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
