HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 22
IDD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN
;
IDD0
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once
every two clock cycles.
Operating Current: one bank; active/read/precharge; Burst = 4;
IDD1
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VILMAX; tCK
tCKMIN
=
IDD2P
IDD2F
Precharge Floating Standby Current: CS ≥ VIHMIN, all banks idle;
CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF
for DQ, DQS and DM.
Precharge Quiet Standby Current:
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs stable
at ≥ VIHMIN or ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current: one bank active; CS ≥ VIHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, IDD3N
DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock
cycle.
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs IDD4R
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs IDD4W
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333; tCK = tCKMIN
Auto-Refresh Current: tRC = tRFCMIN, burst refresh
IDD5
IDD6
IDD7
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; tCK = tCKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for
detailed test conditions.
Data Sheet
66
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
