HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 21
AC Timing - Absolute Specifications PC2100A and PC2100
Symbol –7 –7F
DDR266
Min. Max.
Parameter
Unit Note/
Test Condition
DDR266A
Min. Max.
1)
2)3)4)5)
Auto-refresh to Active/Auto-refresh
command period
tRFC
75
—
75
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
20
—
20
—
ns
tRPRE
tRPST
0.9
1.1
0.9
1.1
tCK
tCK
ns
Read postamble
0.40 0.60
0.40 0.60
Active bank A to Active bank B command tRRD
15
0.25
0
—
—
—
15
0.25
0
—
—
—
Write preamble
tWPRE
tWPRES
tWPST
tWR
tCK
ns
tCK
ns
Write preamble setup time
Write postamble
0.40 0.60
0.40 0.60
Write recovery time
15
1
—
—
—
—
15
1
—
—
—
—
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
tWTR
tCK
ns
tXSNR
tXSRD
75
200
75
200
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR266, DDR266A
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VIH(ac) and VIL(ac)
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Data Sheet
65
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
