HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Timing Diagrams
5
Timing Diagrams
tDQSL
tDQSH
DQS
DQ
tDH
tDS
DI n
tDH
tDS
DM
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Don’t Care
Figure 38 Data Input (Write), Timing Burst Length = 4
DQS
tDQSQ max
tQH
DQ
tQH (Data output hold time from DQS)
t
DQSQ and tQH are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration.
.
tDQSQ and tQH both apply to each of the four relevant edges of DQS.
t
DQSQ max. is used to determine the worst case setup time for controller data capture.
tQH is used to determine the worst case hold time for controller data capture.
Figure 39 Data Output (Read), Timing Burst Length = 4
Data Sheet
69
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
