HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 23
Symbol
IDD Specifications
DDR200
-8
DDR266A
-7
DDR266
-7F
DDR333
-6
DDR400B Unit
-5
Note/Test
Condition1)
2)
typ. max. typ. max. typ. max. typ. max. typ. max.
IDD0
IDD1
70
72
80
83
5
90
75
100
105
110
115
8
83
110
115
120
125
8
85
110
115
120
125
9
70
90
90
mA
mA
x4/x8 3)
x16 3)
x4/x8 3)
x16 3)
3)
95
77
86
88
75
100
105
7
90
98
100
104
6
80
100 mA
110 mA
94
102
6
95
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
6
4
5
mA
mA
mA
mA
mA
mA
3)
3)
3)
3)
30
18
13
40
42
79
89
85
96
126
1.5
35
35
40
35
40
45
55
30
36
28
18
45
54
22
20
25
20
25
25
28
20
16
15
18
15
18
18
21
13
45
50
55
50
55
60
65
38
50
52
60
52
60
63
70
43
x16 3)
x4/x8 3)
x16 3)
x4/x8 3)
x16 3)
IDD4R
IDD4W
95
95
115
130
125
140
180
2.5
95
115
130
125
140
180
2.5
110
124
125
141
144
1.5
140
160
145
165
190
2.5
85
100 mA
120 mA
105 mA
130 mA
190 mA
110
105
120
170
2.5
107
105
119
135
1.5
107
105
119
135
1.5
100
90
100
140
1.4
—
3)
IDD5
IDD6
2.8
mA
mA
standard power3)4)
low power
x4/x8 3)
1.20 1.25 1.20 1.25 1.20 1.25 1.20 1.25
—
IDD7
150
158
210
220
171
180
225
235
171
180
225
235
208
218
270
285
210
210
250 mA
250 mA
x16 3)
1) Test conditions for typical values: VDD = 2.5 V (DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for maximum
values: VDD = 2.7 V, TA = 10 °C
2) IDD specifications are tested after the device is properly initialized and measured at 100 MHz for DDR200, 133 MHz for
DDR266, 166 MHz for DDR333, and 200 MHz for DDR400.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
Data Sheet
67
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
