HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Electrical Characteristics
4.4.1
IDD Current Measurement Conditions
IDD1: Operating Current: One Bank Operation
1. Only one bank is accessed with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are changing
once per clock cycle. lout = 0 mA.
2. Timing patterns
a) DDR200 (100MHz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2 × tCK, tRAS = 5 × tCK
Setup: A0 N R0 N N P0 N
Read : A0 N R0 N N P0 N - repeat the same timing with random address changing
50% of data changing at every burst changing at every burst
b) DDR266 (133MHz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3 × tCK, tRC = 9 × tCK, tRAS = 5 × tCK
Setup: A0 N N R0 N P0 N N N
Read : A0 N N R0 N P0 N NN - repeat the same timing with random address changing
50% of data changing at every burst
c) DDR333 (166MHz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3 × tCK, tRC = 9 × tCK, tRAS = 5 × tCK
Setup: A0 N N R0 N P0 N N N
Read : A0 N N R0 N P0 N N N - repeat the same timing with random address changing
50% of data changing at every burst
d) DDR400B (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRCD = 3 × tCK, tRC = 11 × tCK, tRAS = 8 × tCK
Setup:A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address changing
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
IDD7: Operating Current: Four Bank Operation
1. Four banks are being interleaved with tRCMIN. Burst Mode, Address and Control inputs on NOP edge are not
changing. IOUT = 0 mA.
2. Timing patterns
a) DDR200 (100 MHz, CL = 2): tCK = 10 ns, CL = 2, BL = 4, tRRD = 2 × tCK, tRCD = 3 × tCK, Read with
autoprecharge
Setup: A0 N A1 R0 A2 R1 A3 R2
Read: A0 R3 A1 R0 A2 R1 A3 R2 - repeat the same timing with random address changing
50% of data changing at every burst
b) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, CL = 2, BL = 4, tRRD = 2 × tCK, tRCD = 3 × tCK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
c) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, CL = 2.5, BL = 4, tRRD = 2 × tCK, tRCD = 3 × tCK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
d) DDR400B (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRRD = 2 × tCK, tRCD = 3 *× tCK, tRAS = 8 × tCK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing with random address
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
Data Sheet
68
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
