Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Parameter
CAS
latency
Symbo
l
Limit Values
–11
Unit Note
–10
-14
min
max
min
max
min
max
Power Down Exit time
tXPN
7
—
7
—
8
—
tCK
Other Timing Parameters
RES to CKE setup timing
RES to CKE hold timing
tATS
tATH
tKO
10
10
10
—
—
—
10
10
10
—
—
—
10
10
10
—
—
—
ns
ns
ns
Termination update Keep Out
timing
Rev. ID EMRS to DQ on timing
REV. ID EMRS to DQ off timing
tRIDon
tRIDoff
—
—
20
20
—
—
20
20
—
—
20
20
ns
ns
1) At 1000 MHz speed grade only 1-CS mode is supported
2) DLL on mode
3) Timing is calculated for a clock frequency of 700 MHz
4)
tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs
5) This value of tMRD applies only to the case where the "DLL reset"’ bit is not activated.
6)
7)
8)
t
t
t
MRD is defined from MRS to any other command then READ.
RAS,max is 8×tREFi
CCD is either for gapless consecutive reads or gapless consecutive writes.
9) WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
10) WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
11) This parameter is defined for commands issued to rank m following rank n where m ≠ n. For all other type of access, standard timing
parameters do apply.
12) Please round up tRTW to the next integer of tCK
.
13) This parameter is defined per byte
Rev. 0.92, 2007-10
41
06122007-MW7D-3G3M
QIMONDA [ QIMONDA AG ]
