Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
5.12
AC Timings for HYB18H1G321AF–10/11/14
TABLE 22
Timing Parameters (HYB18H1G321AF–10/11/14 )
Parameter
CAS
latency
Symbo
l
Limit Values
Unit Note
–10
min
–11
-14
max
min
max
min
max
Clock and Clock Enable
1)
System frequency
CL = 12
fCK12
fCK11
fCK9
tCH
450
400
—
1000
900
—
—
—
—
—
MHz
2)
CL =11
CL = 9
400
—
900
—
450
—
700
—
MHz
2)
MHz
3)
Clock high level width
Clock low level width
0.45
0.45
0.45
0.55
0.55
—
0.45
0.45
0.45
0.55
0.55
—
0.45
0.45
0.45
0.55
0.55
—
tCK
3)
tCL
tCK
3)4)
Minimum clock half period
tHP
tCK
Command and Address Setup and Hold Timing
Address/Command input setup
time
tIS
0.24
—
0.27
—
0.35
—
ns
ns
Address/Command input hold time tIH
0.24
0.7
—
—
0.27
0.7
—
—
0.35
0.7
—
—
3)
Address/Command input pulse
width
tIPW
tCK
Mode Register Set Timing
5)6)
Mode Register Set cycle time
tMRD
6
—
—
6
—
—
6
—
—
tCK
5)
Mode Register Set to READ timing tMRDR
12
12
12
tCK
Row Timing
Row Cycle Time
Row Active Time
tRC
37
23
9
—
—
—
35
22
8
—
—
—
34
22
7
—
—
—
tCK
7)
tRAS
tRRD
tCK
ACT(a) to ACT(b) Command
period
tCK
ACT(a) to ACT(b) Command
period (different rank)
tRRD_RR
tRP
—
—
1
—
1
—
tCK
Row Precharge Time
14
—
—
13
12
—
—
12
11
—
—
tCK
tCK
Row to Column Delay Time for
Reads
tRCDRD 13
Row to Column Delay Time for
Writes
tRCDWR
t
RCDWR(Min) = max(tRCDRD(Min) - (WL + 1) × tCK;2×tCK
)
tCK
tCK
Four Active Windows within Rank tFAW
36
—
35
—
35
—
Column Timing
8)
CAS(a) to CAS(b) Command
period
tCCD
tWTR
BL/2
7
—
—
BL/2
6
—
—
BL/2
6
—
—
tCK
9)
Internal write to Read Command
Delay
tCK
Rev. 0.92, 2007-10
39
06122007-MW7D-3G3M
QIMONDA [ QIMONDA AG ]
