HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.2.2
Self Calibration for Driver and Termination
The ouput impedance is updated during all AREF commands. These updates are used to compensate for
variations in supply voltage and temperature. Impedance updates do not affect device operation. No activity on
the Address, command and data bus is allowed during a minimum Keep Out time tKO after the Autorefresh
command has been issued.
CLK#
CLK
Com.
Add.
DQ
ARF
NOP
ARF: Autorefresh
Don't Care
tKO
Keep Out time
Figure 12 Termination update Keep Out time after Autorefresh command
To guarantee optimum driver impedance after power-up, the needs 700 cycles after the clock is applied and
stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 700 cycles, but
optimal output impedance will not be guaranteed.
The GDDR3 Graphics RAM proceeds in the following manner for Self Calibration:
The PMOS device is calibrated against the external ZQ resistor value. First one PMOS leg is calibrated against
ZQ. The number of legs used for the terminators ( DQ and ADD/CMD) and the PMOS driver is represented in
Table 16. Next, one NMOS leg is calibrated against the already calibrated PMOS leg. The NMOS driver uses 6
NMOS legs.
Data Sheet
34
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
