HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.2
Programmable impedance output drivers and active terminations
GDDR3 IO Driver and Termination
4.2.1
The is equipped with programmable impedance output buffers and active terminations. This allows the user to
match the driver impedance to the system impedance.
To adjust the impedance of DQ<0:31> and RDQS<0:3> , an external precision resistor (ZQ) is connected between
the ZQ pin and VSS. The value of the resistor must be six times the value of the desired impedance. For example,
a 240 Ω resistor is required for an output impedance of 40 Ω. The range of ZQ is 210 Ω to 270 Ω, giving an output
impedance range of 35 Ω to 45 Ω (one sixth the value of ZQ within 10%).
The value of ZQ is used to calibrate the internal DQ termination resistors of DQ<0:31>, WDQS<0:3> and
DM<0:3>. The two termination values that are selectable using EMRS[3:2] are ZQ / 4 and ZQ / 2.
The value of ZQ is also used to calibrate the internal address command termination resistors. The inputs
terminated in this manner are A<0:11>, CKE, CS, RAS, CAS, WE. The two termination values that are selectable
upon power up (CKE latched LOW to HIGH transition of RES) are ZQ/2 and ZQ.
RES, MF, CLK and CLK are not internally terminated.
If no resistance is connected to ZQ, an internal default value of 240 Ω will be used. In this case, no calibration will
be performed.
VDDQ
ZQ/4 or ZQ/2
Terminator when
Read to
receiving
other Rank
Output Data
Read Data
Enable
DQ
ZQ/6 Driver
when transmitting
VSSQ
Figure 11 Output Driver simplified schematic
Table 14
Parameter
Range of external resistance ZQ
Symbol
min
nom
max
Units
Notes
External resistance value
ZQ
210
240
270
Ω
Table 15
Ball
Termination Types and Activation
Termination type
No termination
Add / CMDs
DQ
Termination activation
CLK, CLK, RDQS<0:3>, ZQ, RES, MF
CKE, CS, RAS, CAS, WE, BA0 - BA2, A<0:11>
DM<0:3>, WDQS<0:3>,
Always ON
Always ON
DQ<0:31>
DQ
CMD bus snooping
Data Sheet
33
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
