HYB18H512321AF
512-Mbit GDDR3
Boundary Scan
3.3.3
Scan Exit Sequence
Figure 9 shows the Scan exit Sequence. This figure show the exiting of the boundary scan functionality in
conjugation with the appended regular SGRAM initilization sequence to bring the SGRAM again in a well defined
state.
stable clock
CLK/
CLK#
tRESL
RES
tATS tATH
Standard Power up sequence
starting with PRE ALL
CKE
tSN
SEN
SOUT
invalid
700tck
Figure 9
Boundary Scan Exit Sequence
Table 13
Parameter
Scan AC Electrical Parameters
CAS latency
Symbol
Limit Values
Unit
Notes
min
max
tRESL
tSN
tRESL
tSN
20
20
-
-
ns
ns
Data Sheet
30
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
