HYB18H512321AF
512-Mbit GDDR3
Functional Description
4
Functional Description
4.1
Initialization
The HYB18H512321AF must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation or permanent damage to the device.
The following sequence is highly recommended for Power-Up:
1. Apply power (VDD, VDDA, VDDQ, VREF). Apply VDD before or at the same time as VDDQ, apply VDDQ before or at
the same time as VREF. Maintain RES=L and CS=H to ensure that all the DQ ouputs will be in HiZ state, all
active terminations off and the DLL off. All other pins may be undefined.
2. Maintain stable conditions for 200 µs minimum for the to power up.
3. After clock is stable, set CKE to High or Low. After tATS minimum set RES to high. On the rising edge of RES, the CKE
value is latched to determine the address and command bus termination value. If CKE is sampled LOW the address
termination value is set to ZQ / 2. If CKE is sampled HIGH, the address and command bus termination is set to ZQ.
4. After tATH minimum, set CKE to high.
5. Wait a minimum of 700 cycles to calibrate and update the address and command termination impedances.
Issue DESELECT on the command bus during these 700 cycles.
6. Apply a PRECHARGE ALL command, followed by an Extended Mode Register command after tRP is met and
activate the DLL.
7. Issue an Mode Register Set command after tMRD is met to reset the DLL and define the operating parameters.
8. Wait 1000 cycles of clock input to lock the DLL. No Read command can be applied during this time. Since the impedance
calibration is already completed, the DLL mimic circuitry can use the actual programmed driver impedance value.
9. Issue a PRECHARGE ALL command or issue 8 single bank PRECHARGE commands, one to each of the
8 banks to place the chip in an idle state.
10. Issue two or more AUTO REFRESH commands.
Data Sheet
31
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
