HYB18H512321AF
512-Mbit GDDR3
Functional Description
VDD
VDDQ
VREF
tATS tATH
RES
CKE
CLK#
CLK
Com
.
DES
DES
PA
EMR
MRS
PA
ARF
ARF
ACT
DM
A0-A7,
A9-A11
CODE
CODE
CODE
CODE
RA
RA
All Banks
All Banks
A
8
BA0 = H, BA0 = L,
BA1 = L BA1 = L
BA0,
BA1
RA
RDQS
WDQS
DQ
t
t
t
t
t
t
min. 200 µs
700 cycles
RFC
1000cycles
PA: PREALL command
RFC
RP
MRD
MRD
RP
VDD and
CLK stable
MRS: MRS command
with DLL Reset
EMR: EMRS command
DES : Deselect
ARF: AUTO REFRESH command
A.C.: Any command
Don't Care
Figure 10 Power Up Sequence
Data Sheet
32
Rev. 1.73, 2005-08
05122004-B1L1-JEN8