HYB18H512321AF
512-Mbit GDDR3
Functional Description
Table 16
Number of Legs used for Terminator and Driver Self Calibration
Termination
Number of Legs Notes
CKE (at RES)
Terminator
ADD / CMD
DQ
0
1
ZQ/2
ZQ
2
1
EMRS[3:2]
1)
00
10
11
Disabled
ZQ/4
ZQ/2
0
4
2
Driver
PMOS
NMOS
ZQ/6
ZQ/6
6
6
1) EMRS[3:2] = 00 disables the ADD and CMD terminations as well.
Figure 13 represents a simplified schematic of the calibration circuits. First, the strength control bits are adjusted
in such a way that the VDDQ voltage is divided equaly between the PMOS device and the ZQ resistor. The best
bit pattern will cause the comparator to switch the PMOS Match signal output value. In a second step, the NFET
is calibrated against the already calibrated PFET. In the same manner, the best control bit combination will cause
the comparator to switch the NMOS Match signal output value.
VDDQ
VDDQ
NMOS
Calibration
Strength
VSSQ
Control [2:0]
PMOS
Calibration
Match
VDDQ / 2
Strength
Control [2:0]
ZQ
Match
VDDQ / 2
VSSQ
VSSQ
Figure 13 Self Calibration of PMOS and NMOS Legs
Data Sheet
35
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
