HYB18H512321AF
512-Mbit GDDR3
Boundary Scan
VDD
VDDQ
VREF
tSDS tSDH
VALID
CLK/CLK#
tSCS
tSCH
SSH[RES]
tSCS
tSCH
SEN
tSES
SCK[CS#]
SOE[MF]
tSCS
tSCS
SOUT[WDQS]
tSDS tSDH
Scan Out Bit 0
Pins
Under
Test
VALID
T=200µs
BoundaryScan Mode
Power-up:
Don't Care
VDD /VDDQ/VREF stable
Figure 7
Scan Initialization for Stand-Alone mode
3.3.2
Scan initilization in regular SGRAM operation
The initilization sequence of the boundary scan functionality in regular SGRAM operation has to follow the given
sequence.
Sequence Flow:
1.) external Voltages (VDD/VDDQ/VREF) need to be stable for 200us, RES has to be kept low, external clock
has to be stable prior to RES goes high
2.) bring RES high and keep clock stable for 700tcks, CKE will be latched by rising RES edge, keep tATH/tATS
3.) bring SEN up to high state to enter boundary scan functionality
4.) operate boundary scan functionality accordingly to the scan features given in Chapter 3.2
5.) boundary scan can be exited by bringing SEN low
6.) wait tSN for bringing up RES, prior to bringing RES to high state external has to be stable
7.) after RES is at high state wait 700tck
8.) continue with regular initilization sequence (PRE-ALL, EMRS, MRS)
The steps 1 and 2 are necessary to enable the termination for the command/address pins. They are part of the
regular SGRAM initilization. They are required if the user wants to issue commands between to entering of the
boundary scan functionality and the power-up sequence. The entering of the boundary scan mode is resetting the
command/address termination values and all EMRS/MRS settings. Therefore they have to be initilized again after
the boundary scan functionary has been left. Figure 8 shows the scan initilization sequence for regular SGRAM
operation.
Data Sheet
28
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
