RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Name
Size Field
Description
DivXCore[4:0]
5
54:50
Processor core logic clock divisor from processor core
fundamental clock.
0: Reserved (DivideBy2)
1: Reserved (DivideBy3)
2: Reserved (DivideBy4)
3: Reserved (DivideBy5)
4: Reserved (DivideBy6)
5: Reserved (DivideBy7)
6: Reserved (DivideBy8)
7: Reserved (DivideBy9)
8: Reserved (DivideBy10)
9: Reserved (DivideBy11)
a: Reserved (DivideBy12)
b: Reserved (DivideBy13)
c: Reserved (DivideBy14)
d: Reserved (DivideBy15)
e: Reserved (DivideBy16)
f: Reserved (DivideBy17)
10: Reserved (DivideBy18)
11: Reserved (DivideBy19)
12: Reserved (DivideBy20)
13: Reserved (DivideBy21)
14: Reserved (DivideBy22)
15: Reserved (DivideBy23)
16: Reserved (DivideBy24)
17: Reserved (DivideBy25)
18: Reserved (DivideBy26)
19: Reserved (DivideBy27)
1a: Reserved (DivideBy28)
1b: Reserved (DivideBy29)
1c: Reserved (DivideBy30)
1d: Reserved (DivideBy31)
1e: Reserved (DivideBy32)
1f: Divide by 1 (DivideBy1)
ClockPbRsvd[3:0]
MBRsvd[2:0]
4
3
2
58:55
61:59
63:62
Reserved, must be set to 0.
Reserved, must be set to 0.
HSTL output delay control.
HSTLCntl[1:0]
Must be set to 01 in HSTL mode.
Must be set to 00 in LVTTL mode.
MBRsvd[45:3]
HSTLCntl[3:2]
43
2
106:64
Reserved, must be set to 0.
108:107 HSTL output delay control.
Must be set to 11 in HSTL mode.
Must be set to 00 in LVTTL mode.
MBRsvd[192:46]
147
255:109 Reserved, must be set to 0.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
52
PMC [ PMC-SIERRA, INC ]
