RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
5.9 Memory Latencies
Table 16 is a compilation of latencies for the different types of on-chip memory accesses for the
E9000. Local cache accesses to the L1 occur at the CPU core frequency, and local L1 misses
access L2 with a 5-cycle miss penalty.
Table 16 On-Chip Memory Latencies
Type of Burst Memory Access
Local L1 Hit
Number of Processor Clocks per Double Word
1-1-1-1
5-1-1-1
Local L2 Hit
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Document No.: PMC-2100294, Issue 2
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