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RM7965A-900UI 参数 Datasheet PDF下载

RM7965A-900UI图片预览
型号: RM7965A-900UI
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor, 64-Bit, 900MHz, CMOS, PBGA256, 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 508 K
品牌: PMC [ PMC-SIERRA, INC ]
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RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet  
5.9 Memory Latencies  
Table 16 is a compilation of latencies for the different types of on-chip memory accesses for the  
E9000. Local cache accesses to the L1 occur at the CPU core frequency, and local L1 misses  
access L2 with a 5-cycle miss penalty.  
Table 16 On-Chip Memory Latencies  
Type of Burst Memory Access  
Local L1 Hit  
Number of Processor Clocks per Double Word  
1-1-1-1  
5-1-1-1  
Local L2 Hit  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2100294, Issue 2  
37  
 
 
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