RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Cache Coherency
Attribute
Read miss
to MM
Store Hit
Store Miss
L2
110: Uncached Non-
Blocking; Uncached.
Reads do not stall
pipeline unless a data
dependency exists.
Strong ordering not
enforced, therefore loads
can be completed out of
program order
-
-
-
-
111: Bypass (Fast
Packet Cache); Bypass
L2
Fill L1
Store L1
Fill L1, Store L1
Bypassed
5.5 Cache Attributes
The RM7965A cache attributes for the instruction, data and internal secondary caches are
summarized in Table 14.
Table 14 RM7965A Cache Attributes
Attribute
Size
Primary Instruction
Primary Data
16 KB
On-chip Secondary
16 KB
4-way
cyclic
256 KB
4-way
cyclic
Associativity
4-way
Replacement
Algorithm
cyclic
Line size
Index
32 byte
vAddr11..0
pAddr35..12
N/A
32 byte
32 byte
vAddr11..0
pAddr15..0
Tag
pAddr35..12
pAddr35..16
Write policy
Read policy
write-back, write-through
block write-back, bypass
N/A
non-blocking
(2 outstanding)
non-blocking (data only, 2
outstanding)
Read order
Write order
critical word first
N/A
critical word first
sequential
critical word first
sequential
N/A
Miss restart
following
complete line
first double (if waiting for
data)
Protection
per word parity
per byte parity
8-bit ECC per DW
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Document No.: PMC-2100294, Issue 2
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