RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
5.2 Data Cache
The E9000 has an integrated 16 KB, four-way set associative data cache that is virtually
indexed and physically tagged. Line size is 32-bytes (8 words). The effective physical index
eliminates the potential for virtual aliases in the cache.
The data cache is non-blocking; that is, a miss in the data cache does not necessarily stall the
processor pipeline. As long as no instruction is encountered that is dependent on the data
reference that caused the miss, the pipeline continues to advance. Once there are two cache
misses outstanding, the processor stalls if it encounters another load or store instruction.
The data array portion of the data cache is 64 bits wide and protected by byte parity while the
tag array holds a 24-bit physical address, 3 control bits, a 2-bit cache state field, and 2 parity
bits.
The most commonly used write policy is write-back, which means that a store to a cache line
does not immediately cause memory to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish
before issuing a subsequent memory operation. Software can, however, select write-through on
a per-page basis when appropriate, such as for frame buffers. Cache protocols supported for the
data cache are as follows:
1. Uncached
Reads to addresses in a memory area identified as uncached do not access the cache. Writes
to such addresses are written directly to main memory without updating the cache.
2. Write-back
Loads and instruction fetches first search the cache, reading the next memory hierarchy
level only if the desired data is not cache resident. On data store operations, the cache is
first searched to determine if the target address is cache resident. If it is resident, the cache
contents are updated and the cache line is marked for later write-back. If the cache lookup
misses, the target line is first brought into the cache, after which the write is performed as
above.
3. Write-through with write allocate
Loads and instruction fetches first search the cache, reading from memory only if the
desired data is not cache resident; write-through data is never cached in the secondary or
tertiary caches. On data store operations, the cache is first searched to determine if the target
address is cache resident. If it is resident, the primary cache contents are updated and main
memory is written, leaving the write-back bit of the cache line unchanged; no writes occur
to the secondary or tertiary caches. If the cache lookup misses, the target line is first brought
into the cache, after which the write is performed as above.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
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