RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
4. Write-through without write allocate
Loads and instruction fetches first search the cache, reading from memory only if the
desired data is not cache resident; write-through data is never cached in the secondary or
tertiary caches. On data store operations, the cache is first searched to determine if the target
address is cache resident. If it is resident, the cache contents are updated and main memory
is written, leaving the write-back bit of the cache line unchanged; no writes occur to the
secondary or tertiary caches. If the cache lookup misses, only main memory is written.
5. Fast Packet Cache™ (Write-back with secondary and tertiary bypass)
Loads and instruction fetches first search the primary cache, reading from memory only if
the desired data is not resident; the secondary and tertiary caches are not searched. On data
store operations, the primary cache is first searched to determine if the target address is
resident. If it is resident, the cache contents are updated, and the cache line marked for later
write-back. If the cache lookup misses, the target line is first brought into the cache, after
which the write is performed as above.
Associated with the data cache is the store queue. When the E9000 executes a store instruction,
this multi-entry queue is written with the store data while the tag comparison is performed. If
the tag matches, then the data is written into the data cache in the next cycle that the data cache
is not accessed (the next non-load cycle). The store queue allows the E9000 to execute a store
every processor cycle and to perform back-to-back stores without penalty. In the event of a store
immediately followed by a load to the same address, a combined merge and cache write occurs
such that no penalty is incurred.
5.3 Secondary Cache
The E9000 has an integrated 256 KB, four-way set associative, and block write-back secondary
cache. The secondary cache has a 32-byte line size, a 64-bit bus width to match the system
interface and primary cache bus widths, and is protected with the same Error Checking and
Correcting (ECC) mechanism used in the R4000 processor. The secondary cache tag array holds
a 20-bit physical address, two control bits, a 3-bit cache state field, and two parity bits.
By integrating a secondary cache, the E9000 is able to decrease the latency of a primary cache
miss without significantly increasing the number of pins and the amount of power required by
the processor. From a technology point of view, integrating a secondary cache leverages CMOS
technology by using silicon to build the structures that are most amenable to silicon technology;
building very dense, low power memory arrays rather than large power hungry I/O buffers.
Further benefits of an integrated secondary cache are flexibility in the cache organization and
management policies that are not practical with an external cache. Two previously mentioned
examples are the 4-way associativity and write-back cache protocol.
A third management policy for which integration affords flexibility is cache hierarchy
management. With multiple levels of cache, it is necessary to specify a policy for dealing with
cases where two cache lines at level n of the hierarchy could possibly be sharing an entry in
level n+1 of the hierarchy.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
32
PMC [ PMC-SIERRA, INC ]
