RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
The E9000 allows entries to be stored in the primary caches that do not necessarily have a
corresponding entry in the secondary. The E9000 does not force the primaries to be a subset of
the secondary. For example, if primary cache line A is being filled and a cache line already
exists in the secondary for primary cache line B at the location where primary A’s line would
reside, then that secondary entry is replaced by an entry corresponding to primary cache line A
and no action occurs in the primary for cache line B. This operation creates the aforementioned
scenario where the primary cache line, which initially had a corresponding secondary entry, no
longer has such an entry. Such a primary line is called an orphan. In general, cache lines at level
n+1 of the hierarchy are called parents of level n’s children.
Another E9000 cache management optimization occurs for the case of a secondary cache line
replacement where the secondary line is dirty and has a corresponding dirty line in the primary.
In this case, since it is permissible to leave the dirty line in the primary, it is not necessary to
write the secondary line back to main memory. Taking this scenario one step further, a final
optimization occurs when the aforementioned dirty primary line is replaced by another line and
must be written back. In this case, it is written directly to memory, bypassing the secondary
cache.
5.3.1
Secondary Caching Protocols
Unlike the primary data cache, the secondary cache supports only block write-back. As noted
earlier, cache lines managed with either of the write-through protocols are not placed in the
secondary cache. A new caching attribute, write-back with secondary and tertiary bypass,
allows the secondary, and tertiary caches to be bypassed entirely. When this attribute is selected,
the secondary and tertiary caches are not filled on load misses and are not written on dirty write-
backs from the primary cache.
5.3.2
Fast Packet Cache Mode
It is possible to bypass the secondary cache using the Fast Packet Cache feature. Fast Packet
Cache can be activated on a per page basis, and allows all accesses into cache, and all write-
backs to use only the primary data cache. This is useful for manipulating transient packet data
and headers without evicting other less transient data from the L2 cache.
Figure 6 illustrates the two level cache hierarchy and shows the tight coupling of the primary
and secondary caches. The primary cache accesses occur at the core frequency.
If there is a primary miss that hits in secondary, then a 5-cycle miss penalty occurs. This latency
is best in class for a processor in this performance range, and helps optimize the E9000 core for
the highest possible performance.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
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