RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Figure 6 Fast Packet Cache Mode
CPU
1-1-1-1 (Core)
5-1-1-1 (Core)
Primary Cache (L1)
Instr 16 KB, Data 16 KB
Secondary Cache (L2)
256KB, 4-way assoc
Fast Packet Cache
(Bypass Mode)
5.4 Cache Modes
Table 13 summarizes the E9000 cache operating modes. The coherency attributes referred to in
Table 13 are written into the TLB entry to program the coherency attribute for that page.
Table 13 E9000 Cache Operating Modes
Cache Coherency
Attribute
Read miss
to MM
Store Hit
Store Miss
L2
000: Write-through No
Fill L1
Store L1and MM
Store to MM
Receives L1
Allocate
displacements
001: Write-through with
Allocate
Fill L1
Store L1 and MM Store to L1 and
MM; Fill L1
Receives L1
displacements
010: Uncached blocking;
Uncached. Reads stall
pipeline. Strong ordering
enforced. Loads and
stores complete in
-
-
-
-
program order
011: Writeback
Fill L1 and L2 Store L1
Store Miss, Hit L2:
Read L2->L1
Store L1
Receives L1
Displacements
Store Miss L1, L2:
Read MM->
L1, L2, Store L1
100: Reserve
101: Reserve
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
34
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